VHDL: is using inout port bad practise?

Question

I have a program where i'm using inout port following way:

port : inout unsigned(9 downto 0);
...
if port > 10 then
   port <= port + 1
end if;

I'm using inout port so i can read output (to realize feedback).

Either there was missunderstanding between me and my teacher, or my teacher is strongly against using inout ports.

I'm used to high-level programming, so it is not odd to me, to write code like that. I'm aware that there is not much of circuits with inout ports on FPGA, but I'm not using it so often and it is just against my sense to split inout port to in and out, just to get the functionality i want, the different way.

I will be glad for your second opinion on using inout ports.

Answer 1

If you are implementing a bidirectional port, then of course inout is the right thing to use!

BUt for reading the value you are outputting to a port, your teacher is right; it is extremely bad practice. (If something else is also driving that port you will see the resolved value instead of the value you want).

That is what "buffer" ports are for.

Unfortunately there has been a lot of odd prejudice against buffer ports, and some tools warn unnecessarily when you use them (though they usually implement them just fine!) and there are some unnecessarily odd rules connecting buffer ports to ports in outer modules.

I can't remember exact details but I believe a buffer port can't connect directly to an output port in the next level up - though VHDL-2002 and newer removed this rule. Even though "buffer" ports are now more readily usable, there is still some reluctance to use them.

As a result of all this, the commonest solution is to use an internal signal e.g. port_int which you can read, and a simple assignment statement to copy it to the actual port.

So VHDL-2008 has removed the restriction prohibiting reading the value being driven to an "out" port, making an "out" port indistinguishable from a "buffer" port.

My preference : use a Buffer port.

If there is some reason preventing this (say a code style guide, or local prevailing opinion), then (a) use "out" ports if your tools support VHDL-2008 or (b) use an internal signal.