I should create an entity in VHDL that has a variable number of inputs and outputs. This number of pins should be given from the GENERIC construct. Let's suppose to have this code:
entity HELLO is
GENERIC(NUM_INPUT: integer:=4;
NUM_OUTPUT: integer:=2
);
port(
input1 : in std_logic_vector(31 downto 0);
input2 : in std_logic_vector(31 downto 0);
input3 : in std_logic_vector(31 downto 0);
input4 : in std_logic_vector(31 downto 0);
out1 : out std_logic_vector(31 downto 0);
out2 : out std_logic_vector(31 downto 0)
);
end entity HELLO;
Obviously, writing them manually(as in example above) make the GENERIC construct useless.
I want that this 4 inputs and 2 outputs are automatically generated in accordance with GENERIC info. How to do?
I think the easiest way to achieve this is to define a custom array type for your 32 bit word in a package, something like:
type WORD_ARRAY_type is array (integer range <>) of std_logic_vector (31 downto 0);
your entity declaration then becomes:
use work.HELLOPackage.all;
entity HELLO is
GENERIC (
NUM_INPUT : integer := 4;
NUM_OUTPUT : integer := 2
);
port (
input1 : in WORD_ARRAY_type(NUM_INPUT-1 downto 0);
out1 : out WORD_ARRAY_type(NUM_OUTPUT-1 downto 0)
);
end entity HELLO;
You could also use unconstrained arrays for the input and output:
entity HELLO is
GENERIC (
NUM_INPUT : integer := 4;
NUM_OUTPUT : integer := 2
);
port (
input1 : in WORD_ARRAY_type;
out1 : out WORD_ARRAY_type
);
end entity HELLO;
then work with these ports using the generics. When instantiating the entity, simply connect an array with the right dimensions to match the generics.
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