scary_jeff questions

scary_jeff answers

• VHDL - Why are you not allowed to use variables in generate loops
• Object is used but not declared?
• Get attribute of a field from a VHDL record type
• Variable number of inputs and outputs in VHDL
• VHDL multiple std_logic_vector to one large std_logic_vector
• How to write an integer to stdout as hexadecimal in VHDL?
• Neon code for converting b/w rectangular and polar forms
• Connecting a STD_LOGIC to a one bit STD_LOGIC_VECTOR