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Why do we use functions in VHDL

Tags:

vhdl

Functions are obviously less verbose to write than entities. But it implies many drawbacks, including:

  • No generic keyword equivalent
  • Only one output possible

It appears that functions can be called recursively. May it not be the case with entities? If so, is there any good reason to use functions except for aesthetic purposes?

like image 964
simon.denel Avatar asked Jan 21 '13 17:01

simon.denel


2 Answers

Functions can't create hardware directly - they have to exist within an architecture to do so. There's nothing to stop you putting all your functionality into a function (or procedure) and then just calling that within a process though.

Regarding some of your other points:

  • With procedures you can have multiple inout or out parameters.

  • Entities can recurse... Consider:

    entity recurse is
        generic (
            depth : integer := 1;
            param : integer := 3);
        port (
            a : in  integer;
            b : out integer);
    end entity recurse;
    
    architecture a1 of recurse is   
        signal c : integer;
    begin
        c <= a + 1;
        bottom: if depth = param generate
            b <= a + 1;
        end generate bottom;
    
        mid:if depth /= param generate
            recurse_1: entity work.recurse
                generic map (
                    param => param,
                    depth => depth+1)
                port map (
                    a     => c,
                    b     => b);
        end generate mid;
    end architecture a1;
    

Not very useful, but it synthesises and simulates just fine.

  • And finally, of course you only use functions for aesthetic purposes (assuming you include maintainability and readability into the definition of aesthetic, which most programming types do in my experience). You only use enumerated types, entities, records and a whole host of other language features for 'aesthetic purposes'. Even assembly mnemonics are aesthetic! Maybe should return to toggling DIP switches :)
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Martin Thompson Avatar answered Oct 11 '22 11:10

Martin Thompson


Functions in vhdl make the code easy to maintain and read. generally architectures are very big and while debugging if something is not working you can easily find the problematic function and correct it and no need to analyse the entire architecture body.

in case of small codes it's useless but in more big machines it makes you better understand if you consider it function wise.

There is no rule for this so all comments are welcome.

in short : the advantage of functions are

  • overloading
  • operators definition
  • overloading of operators therefore
  • Better Structure of code
like image 26
Arpit Avatar answered Oct 11 '22 12:10

Arpit