VHDL: how to set a value on an inout port?

Question

I am trying to test a VHDL component, but I can't seem to get this one inout port to give me any behaviour. I've tried setting the port to everything from '1' to '-', but it still comes up as 'U' in simulation. Any sugestions what might be wrong?

Answer 1

For Inout port (for example in RAM):

....
port(
    data    :inout std_logic_vector (DATA_WIDTH-1 downto 0);
....
-- Memory Write Block
-- Write Operation : When we = 1, cs = 1
  MEM_WRITE: process (address, cs, we, data, address_1, cs_1, we_1, data_1) begin
    if (cs = '1' and we = '1') then
       mem(conv_integer(address)) <= data;
    end if;
  end process;

 -- Tri-State Buffer control
  data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z');

 -- Memory Read Block
  MEM_READ: process (address, cs, we, oe, mem) begin
    if (cs = '1' and we = '0' and oe = '1') then
      data_out <= mem(conv_integer(address));
    else
      data_out <= (others=>'0');
    end if;
  end process;

You assign data read and write for inout with a condition. When data is read, it is driven by another module. When it writes, it is driven by internal.

• When driven by another module (as in signal), data is resolved between all 'Z' and a vector "0101010" for example. The data will driven as "0101010".
• In the other case: the other module must drive data by all "Z" and then the internal signal can put its value to data.

Answer 2

You need an explicit driver to 'Z'.

Answer 3

I've tried setting the port to everything from '1' to '-', but it still comes up as 'U' in simulation.

As an aside to the good answer on assigning/reading inout ports, the above quoted text could be related to the port being assigned to in two separate places, so it's resolved as 'U'.