VHDL configurations can be used to bind components to entities with a different name, and even with completely different ports. [see this article for more info]
configuration c2 of testbench is
for str
for dut_inst : dut
use entity work.unrelated(rtl)
port map(
port1 => a,
port2 => b,
port3 => c,
port4 => "unused"
);
end for;
end for;
end configuration c2;
Have any of you ever seen this happen in a commercial project project? What was the purpose for dropping in a seemingly unrelated entity? Why did they not just change the instantiation code?
I can make up hypothetical situations, but I'm interested in a real-life use case.
Never seen the port bindings change, but I have seen it used to bind in different versions of components with the same port map. Some examples I've seen:
None of these need the features you're talking about though. The only thing I can think of that using a different component might be useful for is if you've got something like multiple RAM library vendors, and need to swap between them regularly. Even then it's unlikely you're going to be able to do a one-for-one port mapping. There's always a power-down pin that needs inverting or something.
No, I've never seen that in the wild.
I guess the reason is that most people (myself included) don't even know that such things are possible with configurations.
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With