How to manage large VHDL testbenches

Question

One problem I've seen again and again on different VHDL projects is that the top-level testbenches are always large and difficult to keep organized. There is basically a main test process where EVERY test signal is controlled or validated from, which becomes HUGE over time. I know that you can make testbenches for the lower-level components, but this question mainly applies to top-level input/output tests.

I'd like to have some kind of hierarchy structure to keep things organized. I've tried implementing VHDL procedures, but the compiler was very unhappy because it thought I was trying to assign signals from different sections of code...

Is there anything available in VHDL to achieve the behavior of c programming's inline-function or #define preprocessor replacement macros? If not, what can you suggest? It would make me happy to be able to have my top-level test bench look like this:

testClockSignals();
testDigitialIO();
testDACSignals();
...

Having the implementation of these functions in a separate file would be icing on the cake. Haha...I'd just like to write and simulate the test benches in C.

Answer 1

It is a VHDL requirement that the either you write the procedures in the process (as @MortenZdk suggests) or you pass all the IO to it.

My preference is to put my procedures only in packages, so I use the pass all IO approach. To simplify what is passed, I use records. If you reduce it to one record, it will be inout and require resolution functions on the elements of the record.

For more ideas on this approach, goto: http://www.synthworks.com/papers/ and see the papers titled: "Accelerating Verification Through Pre-Use ..." (near the bottom) and " VHDL Testbench Techniques that Leapfrog SystemVerilog" (at the top)

Another key aspect is to use a separate process for each independent interface. This way stimulus can be generated concurrently for different interfaces. This is also illustrated in the papers.