Is there any free program out there that can parse a collection of VHDL files and build a block diagram from them?
I'm looking more for a program that will build a block diagram image to go along with the documentation for the hierarchy, similar to the way javadoc builds a class diagram after parsing the documentation for a series of classes.
Altera's Quartus can compile VHDL and provide you with the top-level schematic blocks, representing the VHDL signals. Ditto with Xilinx ISE. Its not open source software, but it is free to download and use.
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