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Currently, I am learning some FPGA design techniques using VHDL, my problem is whether we can use := and <= interchangeably in VHDL or not, though I've seen the use of := in constants declarations and <= in assignments? Thanks in advance!
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Assignment Symbol in VHDL Also note that <= is also a relational operator (less than or equal to). This is syntax dependent. If <= is used in any conditional statement (if, when, until) then it is a relational operator, otherwise it's an assignment.
Signal and variable are two objects in VHDL programming. However, the main difference between signal and variable in VHDL is that a signal is an object with a past history of values, while a variable is an object with a single current value.
14. What is the difference between SIGNAL and VARIABLE? Explanation: SIGNALs are used to pass information between entities, they act as interconnection between different entities whereas VARIABLEs can be used in the process or subprogram in which it is declared.
Variables are local to a process. They are used to store the intermediate values and cannot be accessed outside of the process. The assignment to a variable uses the “:=” notation, whereas, the signal assignment uses “<=”.
The rules are a little more complex than this, but basically: you use <= to do signal assignment, which takes effect on the next delta cycle. You use := to do variable assignment, which takes place immediately. So if you have a signal, you always use <=. If you have a variable, you always use :=.
Some places where this is not quite that case that you will commonly run into, for instance, initialization, where := is used even for signals.
So:
signal some_signal : std_logic := '0'; -- 0 initial value
...
variable some_variable : std_logic := '0'; -- 0 initial value
...
some_signal <= '1'; -- will assign 1 at the next time step (delta cycle)
...
some_variable := '1'; -- assigns 1 immediately
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