VHDL and Verilog serve the same purpose, but most engineers favor one of both languages. I want to find out who favors which language.
There are dozens of myths and common wisdoms about the separation between Verilog and VHDL. (ASIC / FPGA, Europe / USA, Commercial / Defense, etc.) If you ask around, people will tell you the same thing over and over, but I want to find out if these myths are based on reality.
So my question: can anybody provide sources of quantitative data that indicate who uses VHDL and who uses Verilog? Again, I’m looking for numbers, not for gut feelings and general indications.
VHDL and Verilog are both fairly new and fairly specialized languages. Those two characteristics make their qualitative data hard to come by. On the other hand, we can use these characteristics to our advantage. We can attempt to infer the popularity of these languages based on the number of references that are available.
Amazon.com Book Listings By Subject
VHDL 315
Verilog 132
Google Trends: Verilog (red) vs VHDL (blue) - Source
By these numbers (and only these numbers) VHDL seems to be more widely-used than Verilog; however, there is no indication on the market share details of each.
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