Hidden Features of VHDL [closed]

Question

The original question was:

What are some really useful but esoteric language features in VHDL that you've actually been able to employ to do useful work?

The original question was deleted, and I was just answering. I think this is an interesting question, especially when you compare VHDL to other (normal) programming languages.

Disclaimer: I only did few trivial examples in VHDL.

But what I especially liked, when compared to other programming languages (which is probably not what you are asking about, but I think just for these things every programmer should know VHDL a bit):

1. The ability to have several different implementations (architectures) of a single interface, and exchange them easily.

2. The low-overhead parallelism inherent to the language model. It sort of reminds me of dataflow languages.

Answer 1

What are some really useful but esoteric language features in VHDL...

User-defined physical types like "angle", "voltage", "temperature_coefficient", where you can then write stuff like temp <= 45 deg; or volt <= 3.3 V;.

Answer 2

Sometimes, there are more than one way to do something. OK, most of the time, you can do things in many ways in VHDL. Look at situation where you want to assign different values to a signal, based on the value of another signal.

Selected Signal Assignment

The most specific way to do this is with as selected signal assignment. Based on several possible values of b, you assign a value to a. No redundancy in the code here.

with a select b <=
        "1000" when "00",
        "0100" when "01",
        "0010" when "10",
        "0001" when "11";

Conditional Signal Assignment

The construct of a conditional signal assignment is a little more general. For each option, you have to give a condition. This means that you could write any boolean expression as a condition, which give you more freedom than equality checking. While this construct would give you more freedom, there is a bit more redundancy too. We had to write the equality check (a =) on every line. If you use a signal with a long name, this will make your code bulkier. Also, the separator that's used in the selected signal assingment was a comma. In the conditional signal assingment, you need the else keyword. More code for the same functionality.

b <= "1000" when a = "00" else 
         "1000" when a = "01" else 
         "1000" when a = "10" else 
         "1000" when a = "11";

Combinational Process with Case Statement

The most generally usable construct is a process. Inside this process, you can write a case statement, or a cascade of if statements. There is even more redundancy here. You the skeleton code for a process (begin, end) and the sensitivity list. That's not a big effort, but while I was drafting this, I had put b in the sensitivity list instead of a. Easy to make a small misstake. You also need to specify what happens in the other cases.

process(a)
begin
        case a is
                when "00" => b <= "1000";
                when "01" => b <= "0100";
                when "10" => b <= "0010";
                when "11" => b <= "0001";
                when others => assert "unreachable" severity failure;
        end case;
end process;

While this last code snippet is the largest and perhaps most error-prone, it is probably also the most common. It uses two familiar and often-used constructs: the process and the case statements.

The problem with the selected and conditional signal assignments is that there is no system in their syntax. The meaning is almost identical, but the syntax is just different enough to throw you off. I know many engineers who permanently have a copy of the Doulos Golden Reference Guide to VHDL lying on their desks. Which is good for Doulos, because their name gets mentioned all the time.

Answer 3

The best feature of VHDL — that it is used to design and implement hardware. :)

The ability to have several different implementations (architectures) of a single interface, and exchange them easily.

The same with OOP in C++: you can define one interface and many implementations. It is very useful in VHDL to create simulation and synthesis models for the same device.

The low-overhead parallelism inherent to the language model. It sort of reminds me of dataflow languages.

Actually, there is SystemC library to C++ which implements parallel execution semantics. You can easily download and try this: http://www.systemc.org. I'm working on C++-to-RTL synthesis. So I hope in 4-5 years all hardware development will be done using SystemC and C++.

Answer 4

What are some really useful but esoteric language features in VHDL

Firstly, I don't buy into the theory that VHDL has 'esoteric' features. However, the prevalent 'styles' of VHDL that exist in the wild are most often influenced by what subset of VHDL is supported by hardware synthesizers.

The equation in the VHDL world is very simple: if tools support a language subset, it will be used. If not, the feature will likely be underused.

especially when you compare VHDL to other (normal) programming languages.

Note that VHDL is not a programming language. Rather, it is a language for describing discrete event systems (with an 'accidental' consequence that it can be used to describe digital hardware). I suppose that the comparison to programming languages stems from VHDL looking like some actual programming languages.

Now on to some actual answers to the OP's question.

What are some really useful but esoteric language features in VHDL...

Here's my pick, in no particular order.

1. Architectures: By far, the ability to select different architectures for an interface is the most useful feature VHDL has and which is being used at all times.
2. Generators: using generators you can pretty easily describe complex regular hardware structures. Think multipliers, adders, complex pipelines and the like. Unfortunately, many tools make a mess out of the generated output.
3. Blocks: A cheap way to sub-divide your design into sub-blocks; not all tools support it though.
4. Signal resolution: Rather useful when simulating circuits and the like, not so for hardware synthesis.
5. Attributes: A great way to attach instructions to the simulator/synthesizer to help it out in finding the best way to implement your circuit. While this can in most cases be done with command line options to the synthesizer/mapper/p&r tools, attributes feel much more natural, as all the info needed to produce your piece of hardware is confined to a single place.

Answer 5

Quite a few of VHDL's "esoteric" features have their origin in Ada. I mention this because I'm not an Ada expert, but learning Ada has greatly improved my vision of what can be accomplished in VHDL.