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I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this example here:
...
signal x,y,z : bit;
...
process (y)
begin
x<=y;
z<=not x;
end process;
The example says this:
If the signal y changes then an event will be scheduled on x to make it the same as y. Also, an event is scheduled on z to make it the opposite of x. The question is, will the value of z be the opposite of y? Of course, the answer is no, because when the second statement is executed, the event on x has not been processed yet, and the event scheduled on z will be the opposite of the value of x before the process begins.
Well, I need to understand some things:
x is updated as the first statement. This does not still change the value of x, this change is put in a queue to be executed after the process ends. So everything after this statement x <= y will not see the change and will see x having its old value. Is this correct?z. The same here, z will not change its value but it depends on the value of another process. The change on z will be put in queue to be executed at the end of the process. Is this correct?What does happen at the end of the process?
Possibility number 1) The value in x is changed so x has its new value. The second signal z is updated, the first signal x was updated and, given that z depends on x, its value is changed basing on the NEW UPDATED value of x. And the example should work fine.
Possibility number 2) The value in x is changed so x has its new value. The second signal z is updated. Given that z was assigned an old value of x, that's the value that z will hold, the old value of x which was updated, but this update is not considered.
Could you please tell me which one is the correct way?
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A selected signal assignment is a clear way of assigning a signal based on a specific list of combinations for one input signal. The syntax is demonstrated in the example below. The signal name after with is the signal whose values are used to assign the output signal.
A signal can only communicate between sequential statements in the same process by encountering a wait statement. A signal today would be declared in an enclosing declarative region (a block declarative item or a port declaration) or made visible by a use clause when declared as a package declarative item.
Variables are assigned using the := assignment symbol. Signals are assigned using the <= assignment symbol. Variables that are assigned immediately take the value of the assignment. Signals depend on if it's combinational or sequential code to know when the signal takes the value of the assignment.
VHDL assignments are used to assign values from one object to another. In VHDL there are two assignment symbols: <= Assignment of Signals := Assignment of Variables and Signal Initialization.
Variables get updated as you assign them. Signals get update in the next delta cycle (at the earliest).
a := '1'; -- variable
assert a = 1;
b <= '1'; -- signal
computationUsing(b); --reads old value of b
-- new value will be visible after this process ends or some time passes
Jan Decaluwe explains this stuff in more detail here: http://www.sigasi.com/content/vhdls-crown-jewel
106
The way it works:
Y changes and the process begins.
X will be assigned to what Y's value currently is, but not until the end of the process
Z will be assigned to not X's old value but not until the end of the process
The process ends so now X and Z will be updated
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