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New posts in computer-architecture

How to find number of conflict misses in a cache simulator

Adding two vector in assembly x86_64 with AVX2 plus technical clarifications

Vectored interrupts

Is this a mistake in my Computer Architecture book?

computer-architecture

Why are there (load byte unsigned) and (load byte) instructions in MIPS but only (store byte)?

What is PDE cache?

it is possible to run without virtual memory at all, just physical memory (in fact, most embedded systems run this way). How?

Understanding how EIP (RIP) register works?

Interpretation of perf stat output

what happens when one says a computer 'Hangs' or freezes?

perf stat gives different number of instruction for every run

Compile c++ files for all iOS architectures

MIPS memory execution prevention

Which cards and compute capabilities are required to fully utilize CUDA 5's features [closed]

Does the PIC handle non-maskable interrupts?

Hit and miss ration in cache and average time calculation

Cache and scratchpad memories

Analyse code for spatial and temporal locality

How to optimize an algorithm for a given multi-core architecture

Floating point calculations in a processor with no FPU