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Is there a separate communication bus for non-maskable interrupts that bypasses the programmable interrupt controller?
Or does the PIC manage all interrupts but passes all non-maskable ones along by convention?
Is this dependant of the architecture or are there specific reasons to prefer one over the other in general?
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Detailed Solution. Out of these, TRAP is non-maskable and remaining all are maskable interrupts.
On some systems, a computer user can trigger an NMI through hardware and software debugging interfaces and system reset buttons. Programmers typically use debugging NMIs to diagnose and fix faulty code. In such cases, an NMI can execute an interrupt handler that transfers control to a special monitor program.
Non-Maskable Interrupts are those which cannot be disabled or ignored by microprocessor. TRAP is a non-maskable interrupt. It consists of both level as well as edge triggering and is used in critical power failure conditions.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority.
My answer is from some hardware experience that I gained while designing computers a long long time ago in a galaxy far away ... so long ago that I thought I should get a bit of help from a reference. I discovered a place to download Intel's ia32 64 bit system software development manual when I was perusing SO here.
The answer to your first question is that the NMI is a pin on the processor which is isolated from the maskable interrupts which are configured with the PIC.
The answer to your second question is that the PIC doesn't have anything to do with NMI's. However if you have a an APIC, or Advanced Programmable Interrupt Controller, it is possible to generate an NMI as outlined in the manual:
The processor receives a message on the system bus (Pentium 4, Intel Core Duo, Intel Core 2, Intel Atom, and Intel Xeon processors) or the APIC serial bus (P6 family and Pentium processors) with a delivery mode NMI.
The answer to your third question can be seen in the answer to your second. That is, if you have an APIC (not just a PIC) in your hardware. If you want a few more details about how the APIC can send an NMI, have a look at the SO link I've provided. I didn't go into the details here because you were asking about the "lowly" PIC, not the APIC. But just in case I misunderstood you, I think you will find plenty of information on the SO link, and if that is not enough, then go ahead and download the Intel manual.
I hope that clears a few things up. CHEERS!
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