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New posts in memory-model

Concurrent writes to different locations in the same cache line

c++ caching concurrency c++11 memory-model

Are we guaranteed that hashcode caching through data race will work correctly?

.net concurrency volatile memory-model

Does this envelope implementation correctly use C++11 atomics?

c++ multithreading thread-safety memory-model stdatomic

Registers in C#

c# clr cpu-registers memory-model

Will fetch_add with relaxed memory order return unique values?

c++ concurrency atomic memory-model relaxed-atomics

Java memory model : compiler rearranging code lines

java memory memory-model

How to understand the channel communication rules in golang memory model?

go channel memory-model happens-before

Memory barriers and Linux kernel spinlock on TILE-Gx

multithreading linux-kernel memory-barriers memory-model tilera

reordering atomic operations in C++

c++ multithreading memory-model stdatomic

Is this instruction reordering allowed by the JLS or not?

java jvm memory-model jls

Will relaxed memory order lead to infinite loop here?

c++ c++11 concurrency atomic memory-model

What's "sequentially consistent executions are free of data races"?

java memory-model

Why isn't java.lang.Class.newInstance0() strictly correct under the java memory model?

java memory-model

std::atomic<int> memory_order_relaxed VS volatile sig_atomic_t in a multithreaded program

c++ multithreading volatile memory-model stdatomic

fetch_add with acq_rel memory order

c++ atomic memory-model stdatomic

Implicit synchronization when creating/joining threads

c++ multithreading language-lawyer memory-model

Does const_cast ever cause actual code emission?

c++ constants memory-model const-cast data-representation

Concurrency and memory models

language-agnostic concurrency memory-model c++-amp

C11/C++11 weak memory benchmarks

c++ c atomic memory-model stdatomic

Is the transformation of fetch_add(0, memory_order_relaxed/release) to mfence + mov legal?

c++ llvm x86-64 memory-model stdatomic
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