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In the Linux kernel spinlock implementation for the TILE-Gx architecture, it looks like they don't issue any memory barriers when locking (only when unlocking):
https://github.com/torvalds/linux/blob/master/arch/tile/include/asm/spinlock_64.h
Then I don't understand why instructions cannot be reordered above the locking, which would cause instructions believed by the programmer to be executed while holding the lock, to actually execute before the lock is taken?
Other architectures seem to have at least a compiler barrier:
ARM's spinlock has a memory barrier:
https://github.com/torvalds/linux/blob/master/arch/arm/include/asm/spinlock.h
With comment:
A memory barrier is required after we get a lock, and before we release it, because V6 CPUs are assumed to have weakly ordered memory.
And x86's spinlock has a compiler barrier:
https://github.com/torvalds/linux/blob/master/arch/x86/include/asm/spinlock.h
With comment:
barrier(); /* make sure nothing creeps before the lock is taken */
Why is TILE-Gx different? I thought its memory model was as weak as ARM's memory model. And why don't they even have a compiler barrier?
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In computing, a memory barrier, also known as a membar, memory fence or fence instruction, is a type of barrier instruction that causes a central processing unit (CPU) or compiler to enforce an ordering constraint on memory operations issued before and after the barrier instruction.
Spinlock is a locking system mechanism. It allows a thread to acquire it to simply wait in loop until the lock is available i.e. a thread waits in a loop or spin until the lock is available.
If a process tries to execute code which is protected by a spinlock , it will be locked while a process which holds this lock will release it. In this case all related operations must be atomic to prevent race conditions state. The spinlock is represented by the spinlock_t type in the Linux kernel.
The memory barrier instructions halt execution of the application code until a memory write of an instruction has finished executing. They are used to ensure that a critical section of code has been completed before continuing execution of the application code.
The locking function arch_spin_lock uses arch_spin_lock_slow, which in turn uses cmpxchg. The implementation of cmpxchg includes a memory barrier instruction (see http://lxr.free-electrons.com/source/arch/tile/include/asm/cmpxchg.h).
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