Logo Questions Linux Laravel Mysql Ubuntu Git Menu
HTML CSS JAVASCRIPT SQL PYTHON PHP BOOTSTRAP JAVA JQUERY R React Kotlin
 

New posts in cpu-architecture

Is performance reduced when executing loops whose uop count is not a multiple of processor width?

performance assembly x86 cpu-architecture micro-optimization

What is locality of reference?

caching memory cpu-architecture cpu-cache

Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC

performance x86 x86-64 cpu-architecture rdtsc

What is meant by data cache and instruction cache?

assembly arm cpu-architecture cpu-cache

What exactly is a dual-issue processor?

embedded arm pipeline cpu-architecture

Why does breaking the "output dependency" of LZCNT matter?

performance assembly x86 cpu-architecture micro-optimization

Which CPU architectures support Compare And Swap (CAS)?

multithreading multicore atomic cpu-architecture

Temporal vs Spatial Locality with arrays

arrays caching cpu-architecture cpu-cache

Why is the size of L1 cache smaller than that of the L2 cache in most of the processors?

caching memory cpu-architecture processor cpu-cache

Why is Intel Haswell XEON CPU sporadically miscomputing FFTs and ART?

intel cpu-architecture processor avx2

How has CPU architecture evolution affected virtual function call performance?

x86 cpu cpu-architecture virtual-functions branch-prediction

Why is the page size of Linux (x86) 4 KB, how is that calculated?

linux x86 kernel cpu-architecture

How to find the size of the L1 cache line size with IO timing measurements?

c++ c performance caching cpu-architecture

Can x86's MOV really be "free"? Why can't I reproduce this at all?

c assembly x86 cpu-architecture micro-optimization

Undefined symbols for architecture x86_64 on Xcode 6.1

ios xcode cpu-architecture

API call to get processor architecture

android cpu-architecture

Why is __int128_t faster than long long on x86-64 GCC?

c++ performance x86-64 cpu-architecture integer-division

How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent

assembly x86 intel cpu-architecture micro-optimization

what is a store buffer?

architecture hardware intel cpu-architecture

Determining the CPU architecture of a static library (LIB) on Windows

windows 64-bit static-libraries cpu-architecture libpng
« Newer Entries Older Entries »