I have a "watcher" module that is currently using global hierarchies inside it. I need to instantiate a second instance of this with a second global hierarchy.
Currently:
module watcher;
wire sig = `HIER.sig;
wire bar = `HIER.foo.bar;
...
endmodule
watcher w; // instantiation
Desired:
module watcher(input base_hier);
wire sig = base_hier.sig;
wire bar = base_hier.foo.bar;
...
endmodule
watcher w1(`HIER1); // instantiation
watcher w2(`HIER2); // second instantiation, except with a different hierarchy
My best idea is to use vpp (the Verilog preprocessor) to brute-force generate two virtually-identical modules (one with each hierarchy), but is there a more elegant way?
Instantiating Parameterized Modules A parameterized module can be configured by passing values when instantiating the module; After the module name but before the instance name, place a pound-sign followed by a pair of parenthesis. Here the parameters of a module can be changed from their defaults.
Every identifier in Verilog has a unique hierarchical path name, where each module instance, task, function or named begin end or fork join block defines a new level or scope.
Overriding parametersParameters can be overridden with new values during module instantiation. The first part instantiates the module called design_ip by the name d0 where new parameters are passed in within #( ) . The second part uses a Verilog construct called defparam to set the new parameter values.
My preference is to have a single module (or a small number of modules) in your testbench that contains all your probes but no other functionality. All other modules in your testbench that require probes then connect to that "probe module". Use SystemVerilog interfaces in preference to raw wires if that's an option for you. This circumvents your problem since no watcher will require global hierarchies and your testbench on the whole will be considerably easier to maintain. See the Law of Demeter.
Alternatively... (but this puts hierarchy in your instantiations...)
module watcher(sig, bar);
input sig;
input bar;
...
endmodule
watcher w1(`HIER1.sig, `HIER1.foo.bar); // instantiation
watcher w2(`HIER2.sig, `HIER2.foo.bar); // second instantiation, except with a different hierarchy
Subsequently you can also:
`define WATCHER_INST(NAME, HIER) watcher NAME(HIER.sig, HIER.foo.sig)
`WATCHER_INST(w1, `HIER1);
`WATCHER_INST(w2, `HIER2);
Can you use the SystemVerilog bind
keyword to bind the module into every hierarchy that requires it? (This requires that you use SystemVerilog, and have a license for a simulator.)
Using bind is like instantiating a module in the normal way, except that you provide a path to hierarchy into which the module is "remotely" instantiated:
bind top.my.hier my_module instance_name(.*);
bind top.my_other.hier my_module instance_name(.*);
Even better: assume that each hierarchy that you are binding into is a separate instance of the same module. Then:
bind remote_module my_module instance_name(.*);
This binds your module into every instance of the target, no matter where it is in the design. This is very powerful if your module is a verification checker.
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With