In Verilog you enclose code blocks between the words 'begin' and 'end' like this:
if(foo) begin
x <= 1'b0;
y <= 1'b0;
end else begin
x <= x_d;
y <= y_d;
end
Is there any way to set begin and end as parentheses in Emacs, so that you can use check-parens or similar to find any that are mismatched?
I've tried adding this (and variations of) to my ~/.emacs file, but it doesn't like it...
(modify-syntax-entry ?begin "(end" )
(modify-syntax-entry ?end ")begin" )
Thanks.
Sadly, Emacs's parenthesis matching infrastructure doesn't understand much of multi-character tokens. The new library SMIE added in Emacs-23.4 is partly intended to address this issue. It lets major modes describe the syntax of the language (in a very limited kind of grammar) after which things like C-M-f and C-M-b will know how to jump over logical elements, e.g. skip from a begin
to its matching end
. As LindyDancer notes, such things are usually needed for indentation, and indeed the main motivation behind SMIE was to provide a generic indentation engine.
Now Verilog doesn't use SMIE but it does implement similar navigation commands. So you could probably try something like
(defun sm-verilog-check-parens ()
(save-excursion
(goto-char (point-min))
(while (not (eobp))
(verilog-forward-sexp))))
Tho I do not know if verilog-forward-sexp
will give you appropriate warnings/errors if it bumps into the end of buffer at an unexpected moment.
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