Accessing local module variables from test benches in Verilog

Question

When writing a Verilog test bench to verify a module is there any way to access a particular variable local to that module from the test bench?

Answer 1

Use hierarchical reference to access cross-hierarchical variable.

For accessing variable in the sub-hierarchy of current module, you can use relative path, as in example below, "dut.localvar".

For accessing variable of a module which is not part of current module hierarchy, use absolute path from the top, e.g., "testbench.dut.localvar".

module testbench();
reg clk;
wire out;

DUT dut(clk, out);

always@(posedge clk)
begin
   $display("%b", dut.local_var);
end
endmodule

module DUT(input wire clk,output reg out);
reg local_var = 1'b0;

always@(posedge clk)
begin
   local_var = ~local_var;
end
endmodule