What does the term "Verilog Synthesis" mean? [closed]

Question

When someone asks you if you've ever done any verilog synthesis, what does that really mean? Does that mean writing out the code, simulation, downloading the code to the actual hardware, or what? I read it online but they just said it's the process of coverting high level to gate level, which doesn't really tell me much.

Answer 1

Wikipedia answers this question well in its entry "Logic synthesis".

The synopsis is that synthesis transforms high level verilog/vhdl constructs, which don't have real physical hardware that can be wired up to do your logic, into low level logical constructs which can be literally modeled in the form of transistor logic or look-up tables or other FPGA or ASIC hardware components.

Answer 2

Verilog is both a scripting language and a HDL (hardware description language). The scripting component is often used to write testbenches to verify the HDL or (in limited cases) as a metaprogramming language to generate HDL from input parameters. One thing that confuses newcomers is that almost every Verilog tutorial starts out teaching you about the scripting parts of the language. It can act like a simple, imperative, sequential programming language. You can do loops and print results. Almost all of that is irrelevant when you are restricted to the synthesizable subset of Verilog which can be used as an HDL. If someone asks you if you've done Verilog synthesis they are probably trying to distinguish whether you have taken any Verilog designs all the way to actual hardware. Having done so would demonstrate that you understand how to use Verilog as an HDL. If you have only done simulation you may be relying on language features that are not synthesizable and thus not usable in real hardware.