Is there any recommended way to automate module port connection?

Question

I'm trying to understand or research about the best practices of ASIC design in verilog. I'm working on a medium size block with ~20 sub modules (each ~1000 lines of code). It's a painstaking job to manually instantiate all the sub-module and do port connection to create top level RTL.

I want to write a script to automate this. As long as we can define the input/outputs of all the sub-modules and how each sub-modules are connected with each other, it shouldn't be super hard to auto-generate the top level. I don't have enough expertise in design automation though. I was wondering if anyone can give me some pointers about how to get started.

• Is there any open source tool to achieve what I'm trying to do? I didn't find any so far.
• Is there any standardize way to generate synthesizable code of this sort?

I'll highly appreciate any sort of input or advice.

Answer 1

Depending on what text editor you're using, you might be able to use some pre-existing tools. There is an add-on for Emacs that supports auto-instantiating and connecting signals, assuming that you follow certain naming conventions:

http://www.veripool.org/wiki/verilog-mode/Verilog-mode_veritedium

For the vim users out there, there are a couple of plugins that allow using the Emacs script, such as this one:

http://www.vim.org/scripts/script.php?script_id=1875