Passing a hexadecimal value into a module in Verilog

Question

I created a module that accepts a wire [ 4 : 0 ] as input, and I'm using several instances of this module. But, I'm getting:

Syntax error in instance port expression(s)

whenever I pass a value that contains A-F.

For example:

key_schedule i1(09); // works
key_schedule i1(0A); // doesn't work
key_schedule i1(15); // works
key_schedule i1(1D); // doesn't work

If anyone knows what's wrong, I'd appreciate their help.

Also, what happens if I'm passing a value "C", but I also have a wire called C?

Answer 1

Verilog treats all bare numeric literals as decimal. A and D are not legal decimal values.

For hexadecimal literals, you need to specify the literal type using 'h:

key_schedule i1('h0A); // works
key_schedule i1('h1D); // works

Refer to the IEEE Std (1800-2009, for example), section "Numbers".

The following code compiles for me without errors on 2 different simulators (Incisive and VCS):

module tb;
    key_schedule i1(5'h1A);
    key_schedule i2('h1A);
endmodule

module key_schedule (input [4:0] in);
    always @(in) $display(in);
endmodule

Answer 2

From http://www.asic-world.com/verilog/syntax1.html#Integer_Numbers

Verilog HDL allows integer numbers to be specified as

• Sized or unsized numbers (Unsized size is 32 bits)
• In a radix of binary, octal, decimal, or hexadecimal
• Radix and hex digits (a,b,c,d,e,f) are case insensitive
• Spaces are allowed between the size, radix and value

Syntax:

[size]'[radix][value];

Example:

8'h1D;   # 8-bit hex value "1D"