How to remove I/O port declarations using regexp in verilog mode

Question

I'm trying to instantiate abc_d module and i don't want all of its ports to be declared as I/O ports in abc top module. I want to exclude ex_out_port to be declared as output port.

module abc(/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
abc_d u_abc_d(/*AUTOINST*/);
endmodule
//Localvariables:
//verilog-auto-output-ignore-regexp:("ex_out_port")
//END:

expected code:

 module abc (/*AUTOARG*/
 /Inputs
 input port1;
 input port2;
 /Outputs
 output port3;
 output port4;
 /*AUTOWIRE*/
 wire ex_out_port;

 //Instance
 abc_d u_abc_d(/*AUTOINST*/
 .port1 (port1),
 .port2 (port2),
 .port3 (port3),
 .port4 (port4),
 .ex_out_port (ex_out_port)):
endmodule

Related already-answered questions:

• Using Regular Expressions for Verilog Port Mapping
• using emacs auto's to instansiate a stub module (inputs=0, outputs=[]

Answer 1

Your verilog-auto-output-ignore-regexp is slightly off. It works after dropping the parenthesis around "ex_out_port"

//verilog-auto-output-ignore-regexp: "ex_out_port"

I was not able to find any code examples gnore-regexp in documentation or FAQ. I did find one example in a forum on the veriloop site (owners of verilog-mode): https://www.veripool.org/boards/15/topics/1635-Verilog-mode-Scope-for-AUTO_LISP-

---

FYI: Unless you are strictly following Verilog-1995 syntax or running obsolete version of verilog-mode, you can consider change:

module abc(/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/

To an ANSI style header which is supported since Verilog-2001:

module abc(
/*AUTOINPUT*/
/*AUTOOUTPUT*/
);
/*AUTOWIRE*/

It is functionally and behaviorally the same with fewer lines of generated code.