Hardware inspired loop. Nonsense?

Question

The other day I've learnt a cool trick in Verilog. When you need to do something repeatedly. You could use a shift register to count the number of incrementation. Just shifting a 1 from LSB to MSB, and when it reach the MSB you're done.

In C it would be something like this:

for(j=0b1; !(j & (1<<16)); j=j<<1)
{
/*do a thing 16 times*/
}

I know it has limited use because of the bit width, but it isn't involving any addition so it is fast. So my question: Is there any use of this? Is it worth it to use in C or any other high-level language?

Maybe in embedded systems where resources are limited.

Thanks

Answer 1

This is very not worth it. It make the code much less cleaner and harder to read, and the performance difference it negligible.

Your compiler can do these types of optimizations much better than you can. Short loops like this might even be unrolled for performance reasons. However, if you write the loop like that a compiler might not be able to figure that out as easily, so you might even be slowing the program down.

This is really a case of micro-optimization that will almost certainly never make a noticeable difference on your program's runtime.

Answer 2

It seems to me that most of the guys commenting / answering does not really understand what asker is talking about. Verilog language is for hardware design and hardware design is very different thing than software design, no CPU cycles or anything like that. However, short answer is still: No. Long answer:

For sure shifting is MUCH simpler than addition. For shifting there is much less logic from FF (flip flop) to FF. For addition, carry has to be propagated from the LSB bit to the MSB bit, which means log2(N) levels of logic (N is the top value that counter would reach). On the other hand, shift register would use N FFs, while adder would only use log2(N) FFs. So there is a performance / area trade off which also heavily depends on N. Some 'independent' info about adder: http://en.wikipedia.org/wiki/Adder_%28electronics%29 Couldn't find similar article for shifting, but once you understand adder, shifter should be obvious.

This might be important when you are designing the state machine in RTL. But the code you presented has actually nothing to do with the above. This 'for' loop in verilog means all the 'work' will be done in single cycle. So there will actually be N logics. This loop has nothing to do with implementation. It might even only confuse verilog compiler to spit out something strange and affect simulation (where CPU cycles does matter and above answers would be valid). Someone with more experience with tools could comment on that.