Verilog: value(s) does not match array range, simulation mismatch

Question

The following code synthesizes and simulates correctly as far as I can tell, but XST is still giving the following warning: value(s) does not match array range, simulation mismatch. Is there something I'm missing?

Tool used: Xilinx ISE Project Navigator (synthesizer:XST) FPGA: SPARTAN 3E

module error_example(
    input [47:0] data,
    input [2:0] sel,
    output [5:0] data_out
);

   assign data_out = data[sel*6 +: 6];

endmodule

WARNING:Xst:790 - "error_example.v" line 8: Index value(s) does not match array range, simulation mismatch.

Like I said, this works and I've done the math:

sel can have values from 0 to 7,

if sel is 0, then data_out = data[5:0] ...

if sel is 7, then data_out = data[47:42]

Should I do something differently here? Is this a bug in XST?

Answer 1

I have created the example on EDAplayground, which runs without warning.

I would not normally use widths with parameters and if you do you might want to be consistent with the reg definitions.

Try:

1. parameter data = 48'h123456789ABC;
2. parameter [47:0] data = 48'h123456789ABC;

I do not think I have used parameters this way before but declaring a constant reg implies the same logic, which might avoid the warning.

1. reg [47:0] data = 48'h123456789ABC;

NB: It is good practise to use upper case for constants (parameter,localparam).

Alternatively convert to a case statement:

always @* begin
  case (sel)
    3'd0: data_out = 6'dx;
    3'd1: data_out = 6'dx;
    // ...
    default :  data_out = 6'd0;
  endcase
end