What's included in a verilog always @* sensitivity list?

Question

I'm a bit confused about what is considered an input when you use the wildcard @* in an always block sensitivity list. For instance, in the following example which signals are interpreted as inputs that cause the always block to be reevaluated? From what I understand clk and reset aren't included because they dont appear on the right hand side of any procedural statement in the always block. a and b are included because they both appear on the right hand side of procedural statements in the always block. But where I'm really confused about is en and mux. Because they are used as test conditions in the if and case statements are they considered inputs? Is the always block reevaluated each time en and mux change value? I'm pretty much a noob, and in the 3 Verilog books I have I haven't found a satisfactory explanation. I've always found the explanations here to be really helpful. Thanks

module example
( 
    input wire clk, reset, en, a, b,
    input wire [1:0] mux,
    output reg x,y, z
);

always @*    
begin  
 x = a & b;    
  if (en)
    y= a | b;
  case(mux)
    2'b00: z = 0;
    2'b01: z = 1;
    2'b10: z = 1;
    2'b11: z = 0;
  endcase
end
endmodule

Answer 1

Any signal that is read inside a block, and so may cause the result of a block to change if it's value changes, will be included by @*. Any change on a read signal used must cause the block to be re-evaluated, as it could cause the outputs of the block to change. As I'm sure you know, if you hadn't used @* you'd be listing those signals out by hand.

In the case of the code you've provided it's any signal that is:

• Evaluated on the right hand side of an assignment (a and b)
• Evaluated as part of a conditional (en and mux)

...but it's any signal that would be evaluated for any reason. (I can't think of any other reasons right now, but maybe someone else can)

clk and reset aren't on the sensitivity list because they aren't used. Simple as that. There's nothing special about them; they're signals like any other.

Answer 2

In your example, the following signals are included in the implicit sensitivity list:

a
b
en
mux

clk and reset are not part of the sensitivity list.

This is described completely in the IEEE Std for Verilog (1800-2009, for example). The IEEE spec is the best source of detailed information on Verilog. The documentation for your simulator may also describe how @* works.