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Is it possible to take input port as array in verilog?

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verilog

 module median_five(out1,a[0],a[1],a[2],a[3],a[4],en,clka);             
    input [7:0] a[0:4];              
    output out1;              
    endmodule            

**It is giving error.

 module median_five(out1,a,b,c,d,e,en,clka);             
        input [7:0] a,b,c,d,e;              
        output out1;              
        endmodule   

**It is right.

But I want input a,b,c,d,e in array like :

array[0]<=a;            
array[1]<=b;               
array[2]<=c;             
array[3]<=d;            
array[4]<=e;            
like image 397
B.R Avatar asked Apr 02 '16 07:04

B.R


1 Answers

Verilog does not support two dimensional arrays as ports of modules. This feature is supported by SystemVerilog only.

In the first snippet, you are passing two dimensional array a as input, which is not supported. In the latter case, a single dimensional vector is passed to the module which works fine.

It is not clear what you want to do with array. Here are some options. You can declare two dimensional array inside the module itself. Something like follows:

module median_five(out1,a,b,c,d,e,en,clka);
input [7:0] a,b,c,d,e;
output out1;

ref [7:0] array [5]; // array local to module

//always @(posedge clka)  // use non blocking assignments
always @(*)              // use blocking assignments
begin
// .. Some stuff
array[0]=a;            
array[1]=b;               
array[2]=c;             
array[3]=d;            
array[4]=e;     
//..       
end

//.. some other stuff

endmodule 

Another thing you can do is to flatten the array and pass it as inputs. Here, I have flattened each of 8 bit input (a,b,c etc. each) into a single vector (in) and assigned each individual element of array accordingly.

module top (in, out);
  input   [31:0] in; // flattened array as input
  output  [31:0] out;

  wire     [7:0] array [0:3]; // local array

  assign {array[3],array[2],array[1],array[0]} = in;
  //... some operations/procedural blocks etc.
  assign out = {array[3],array[2],array[1],array[0]};
endmodule

Refer to Inputs as two dimensional array link for a similar question. There is a similar blog post too.

like image 195
sharvil111 Avatar answered Nov 19 '22 04:11

sharvil111