How to make the 2-complement of a number without using adder

Question

In two-complement to invert the sign of a number you usually just negate every bit and add 1. For example:

011 (3)
100 + 1 = 101 (-3)

In VHDL is:

a <= std_logic_vector(unsigned(not(a)) + 1);

In this way the synthesizer uses an N-bit adder.

Is there another more efficient solution without using the adder?

Answer 1

I would guess there's not an easier way to do it, but the adder is probably not as bad as you think it is.

If you are trying to say invert a 32-bit number, the synthesis tool might start with a 32-bit adder structure. However then upon seeing that the B input is always tied to 1, it can 'hollow out' a lot of the structure due to the unused gates (AND gates with one pin tied to ground, OR gates with one pin tied to logic 1, etc).

So what you're left with I'd imagine would be a reasonably efficient blob of logic which just increments an input number.

Answer 2

If you are just trying to create a two's complement bit pattern then a unary - also works.

a = 3'b001 ; //        1
b = -a     ; //3'b111 -1
c = ~a + 1 ; //3'b111 -1

Tim has also correctly pointed out that just because you use a + or imply one through a unary -, the synthesis tools are free to optimise this.

A full adder has 3 inputs (A, B, Carry_in) and 2 outputs (Sum Carry_out). Since for our use the second input is only 1 bit wide, and at the LSB there is no carry, we do not need a 'full adder'.

A half adder which has 2 inputs (A, B) and 2 outputs (Sum Carry), is perfect here.

For the LSB the half adders B input will be high, the +1. The rest of the bits B inputs will be used to propagate the Carry from the previous bit.

There is no way that I am aware of to write in verilog that you want a half adder, but any size number plus 1 bit only requires a half adder rather than a fulladder.