what exactly is a variable in VHDL?

Question

I know how to use variables in VHDL and what I can do with that, but I don't know exactly what it is in hardware ?

What is the difference between signals and variables in hardware and where the value of a variable store ? Is it a wire or it depends on my code ?

According to the "QuantumRipple" comments I extend this question :

I synthesized the following simple code with ISE (Xilinx synthesis tool) and the variable (var) synthesized into a D flip flop ??

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY test IS
    port(
        clk    : in  std_logic;
        input  : in  std_logic;
        output : out std_logic
    );
END test;

ARCHITECTURE Behavioral OF test IS
BEGIN
    PROCESS(clk)
        VARIABLE var : std_logic;
    BEGIN
        IF clk'event AND clk = '1' THEN
            var := input;
        END IF;
        output <= var;
    END PROCESS;
END Behavioral;

Thanks for comments and answers ...

Answer 1

Variables can be used in several functionally distinct ways. As a result, the synthesizer can implement them in several ways.

The following applies to clocked processes:

If you independently set the variable in a process before you read it, it will synthesize purely into [a group of] LUTs. (complicated logical functions or a vector variable will require more than one LUT even for a single assignment)

If you update a variable multiple times and read it between updates, it will synthesize into several [groups of] LUTs. This case is no different than if you created a different named variable for each update, read pair.

If you read the value of the variable before it is set in the process and assign it after all reads it will synthesize into a flip flop. Variables in this configuration behave equivalently to signals.

If you set the variable based of a combination of itself and another value before it is independently set, it will synthesize into an (unnamed) flip flop and a [group of] LUTs hanging off of that.

These can also be combined to an extent. For example, if you read a variable at the start of a process and assign it at the end, but also update and read the variable in the middle, it will generate a flip flop whose output is used for the first read, and also some LUTs whose output is used for the second read.

Multiple assignments without intermediary reads also get collapsed into one group of LUTs (nothing taps off of the intermediary value).

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Another important thing to understand about how VHDL is synthesized is that signals and variables do not really get translated into specific things. A signal refers to a specific wire in the design (not the stuff in between like LUTs and Flip Flops). Signals that are assigned in clocked processes will usually refer to the Dout wire from a certain Flip Flop and signals that are assigned in a combinatorial process or concurrent statement will usually refer to a wire coming out of a LUT, although it might refer to the same wire as another signal (including clocked signals!) if there was no logic in the assignment (a simple a <= b).

The assignment statements describe the relationship between wires.

Variables do not refer to a fixed wire, but rather just describe behavior. Each variable assignment that is used to assign something else before it is assigned again creates a reference to a different wire (although these wires will typically not be explicitly named like signal wires - that's the point of variables).

The synthesizer takes that behavior and tries to determine what set of LUTs and Flip Flops are required to make the hardware do that. Note that while signals refer to some fixed wires, they don't refer to all wires. The synthesizer creates many un-named (the synthesizer generates an arbitrary name) wires to connect the generated components (LUTs and flip flops) between each explicitly named wire. It is because variables are so flexible in what the describe (not a fixed wire) that they can cause the generation of so many different combinations of basic components depending on how they are used.

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For your specific code, yes, the variable var will cause a flip flop to be synthesized.

It would also do the exact same thing if 'var' was a signal and the output <= var; assignment was outside of the process.

In your code, var is set based on the sole assignment to refer to the Dout wire of a clocked element (flip flop) that has a Din of input, then the output is assigned to refer to the same wire as var.

In fact, it does the exact same thing as just doing

    IF clk'event and clk = '1' THEN
        output <= input;
    END IF;

in this case, output is just directly assigned to refer to the Dout wire of the clocked element that has a Din of input instead of using var as a proxy.