wait until rising_edge(clk) vs if rising_edge(clk)

Question

I came across two styles of process statements in VHDL.

process(clk)
begin
    if rising_edge(clk)
...do something...

The other one is

process
begin
    wait until rising_edge(clk)
    ...do something...

What are the pros and cons of each method?

Answer 1

Assuming the ... part of the second example does not have any wait statement, the two forms are semantically equivalent.

They will behave identically in simulation.

However, the first form is the recommended style for synthesis and will be deemed more readable by many.

Answer 2

Both forms are equivalent for synthesis in Vivado. The second wait form can be considered more compact as it "saves" an indentation level.