Generic in verilog from a vhdl programmer

Question

What's the equivalent of the generic in verilog? For example

entity my_entity
generic(a : integer);
port(x : in std_logic; y out std_logic);
end entity my_entity;

What's the equivalent for generic? Also what's the equivalent for the if generate and for generate?

Answer 1

The generics are called parameters in Verilog. They are declared within the module by lines like:

parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;

An instantiation may individually refine the parameter values:

my_ram_impl #( 
  .DATA_WIDTH(16), 
  .ADDR_WIDTH(8)
)
ram_instance(
  .clk(clk),
  .addr(addr),
  .data(data),
  .cs(cs),
  .we(we)
); 

Use these directives similar to C for conditional synthesis:

`ifdef  SYM
   ...
`else
   ...
`endif

or, more flexibly generate constructs like:

generate
  if(cond)
    ...
  else
    ...
endgenerate