Syntax for using an array of wires as input

Question

I have the following module:

module add_8bit ( output wire co,
              output wire [7:0] r,

              input wire ci,
              input wire [7:0] x,
              input wire [7:0] y );

I am trying to use it via the following code:

 wire rbit [7:0];
 wire onebit [7:0];
 wire twocomp [7:0];

 wire tco, tci;

 add_8bit t9 ( tco, twocomp, tci, rbit, onebit );

It will NOT compile because of the last line, why?

Thanks.

Answer 1

You've the wire declarations back to front in the second code snippet. Should be:

wire [7:0] rbit;
wire [7:0] onebit;
wire [7:0] twocomp;

Answer 2

In your module definition, you have declared three 8-bit wire ports:

 output wire [7:0] r,
 input  wire [7:0] x,
 input  wire [7:0] y

However, in your calling module, you have declared three 1-bit wide by 8-bit deep wire arrays (refer to the IEEE Standard for Verilog, 1364-2005, Section 4.9 "Arrays):

 wire rbit    [7:0];
 wire onebit  [7:0];
 wire twocomp [7:0];

When you connect these wire arrays to the module instance, port connection type mismatches occur, which result in compile errors.

To fix the situation, you must make sure that the type of the signals used to connect to the instance match the module port type. As Marty pointed out, most likely, you want to change your calling module wire declarations to:

wire [7:0] rbit;
wire [7:0] onebit;
wire [7:0] twocomp;

The other possibility is to change your module ports to match the calling module wires, but I sincerely doubt that is what you want.