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always block @posedge clock

Tags:

clock

verilog

Let's take the example code below:

always @(posedge clock)
   begin
   if (reset == 1)
     begin
        something <= 0
     end
   end

Now let's say reset changes from 0 to 1 at the same time there's a posedge for the clock. Will something <= 0 at that point? Or will that happen the next time there's a posedge for the clock (assuming reset stays at 1)?

like image 282
krabby_snacks Avatar asked Jul 08 '13 19:07

krabby_snacks


Video Answer


1 Answers

It depends on exactly how reset is driven.

If reset and something are both triggered off the same clock, then something will go to 0 one clock cycle after reset goes to 1. For example:

always @(posedge clock)
   begin
   if (somethingelse)
     begin
        reset <= 1;
     end
   end
like image 60
toolic Avatar answered Sep 27 '22 16:09

toolic