Part 1:
I was always told to use functions in Verilog to avoid code duplication. But can't I do that with a module? If my understanding is correct, all functions can be re-written as modules in Verilog except that modules cannot be instantiated from the inside of an always block. Except, in this case, I can always stick with modules. Am I correct?
Part 2:
If I am correct, why can't the Verilog compiler be written in such a way that the modules get the treatment of a function? I mean, why can't the compiler allow the programmer to instantiate a module inside n block and stop supporting functions?
The purpose of a function is to return a value that is to be used in an expression. A function definition always starts with the function keyword followed by the return type, name, and a port list enclosed in parentheses. And it ends with the endfunction keyword.
A function is meant to do some processing on the input and return a single value, whereas a task is more general and can calculate multiple result values and return them using output and inout type arguments. Tasks can contain simulation time consuming elements such as @, posedge and others.
Modules can be instantiated within other modules and ports of these instances can be connected with other signals inside the parent module. These port connections can be done via an ordered list or by name.
Distinctions Between Tasks and FunctionsA function returns a single value; a task does not return a value. The purpose of a function is to respond to an input value by returning a single value. A task can support multiple goals and can calculate multiple result values.
Functions are actually extended expressions and it is used in expressions. It can be used in rhs expression of the 'assign' statement or in expressions inside any procedural block.
Functions cannot consume time.
Functions must return a value.
Modules are used to express hardware hierarchy and contain concurrent procedural blocks (which might contain functions).
Modules may consume time.
Modules cannot return value. (output ports are not return values)
Potentially you can create a function which replaces internals of a single always block and write an equivalent module with an always block which returns function. But this is it.
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