Verilog register cannot be driven by primitives or continuous assignment

Question

I want to use a module in a test bench like this:

reg [31:0] OutputVal;
reg [15:0] InputVal;
sign theSignExtender(InputVal,OutputVal);

When I compile, I get the error:

error: reg OutputVal; cannot be driven by primitives or continuous assignment.

Any suggestions?

Answer 1

Change:

reg [31:0] OutputVal;

to:

wire [31:0] OutputVal;