Are there any grammars for system Verilog that are open source? I'm looking for System Verilog, not plain Verilog grammars.
Verilog-Perl is open source and claims to have SystemVerilog support. You could contact the Perl CPAN author to see if it covers the complete grammar (his email address is listed on the CPAN page).
No(I have looked). In fact very few expensive commercial tools completely support IEEE P1800. There is at least one company that sells a parser API.
Here is a V2K and SV parser in ANTLR grammar.
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