I'd like to do some simulation debugging in Verilog and want to add $display
to some modules. However, I want to be able to track the output a single module provides. I'd like to be able to get the name that the current module was instantiated with to add to the $display
.
For example:
module adder (...)
...
$display($magic_instance_name, " ", in0, " + ", in1);
...
adder memory_address (...);
adder fifo_nvals (...);
And then the output would look like:
memory_address 100 + 8
fifo_nvals 3 + 1
...
One way I could do this is to add an instance_name
parameter to each module. Is there an easier way?
In Verilog jargon, a reference to a lower level module is called a module instance. Each instance is an independent, concurrently active copy of a module.
The module name, formally called an identifier should best describe what the system is doing. Each identifier in Verilog, including module names must follow these rules: It can be composed of letters, digits, dollar sign ($), and underscore characters (_) only. It must start with a letter or underscore.
When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances.
A hierarchical structure is formed when modules can be instantiated inside one another, and hence the top-level module is called the root. Since each lower module instantiates within a given module, which should have different identifier names, there will not be any ambiguity in accessing signals.
You can use %m
to get the full path including the unique instance name:
module tb;
adder memory_address ();
adder fifo_nvals ();
initial #5 $finish;
endmodule
module adder;
initial $display(" hello from ... %m");
endmodule
Prints:
hello from ... tb.memory_address
hello from ... tb.fifo_nvals
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