How can I separate long statements into lines in Verilog

Question

For example, I have a single long statement:

    $display("input_data: %x, 
              output_data: %x,
              result: %x",
              input_data,
              output_data,
              result);

How can I make it into single statement and multiple lines in Verilog?

Answer 1

You need to break up the quoted string. Here is one way:

module tb;

initial begin
    integer input_data  = 1;
    integer output_data = 0;
    integer result      = 55;
    $display("input_data: %x "  , input_data,
             "output_data: %x " , output_data,
             "result: %x "      , result);
end

endmodule

Outputs:

input_data: 00000001 output_data: 00000000 result: 00000037 

Answer 2

From http://www.asic-world.com/systemverilog/literal_values4.html

string  a;
a = "This is multi line comment \
     and this is second line";

/*

Outputs:

a = This is multi line comment^M
        and this is second line

*/

//You will have ^M which is the dos character for new line. If you want to avoid that, then the next solution should be used

string tmg ={" \n"                                               ,
    "//periodic signal intf.KEYCONTROL_CLK \n"         ,
    "fork\n"                                           ,
    "   begin\n"                                       ,
    "     the_clock = 0;\n"                            ,
    "     forever begin\n"                             ,
    "       if(the_clock == 0)\n"                      ,
    "          #(5000000/2 * 1ps);\n"                  ,
    "       else\n"                                    ,
    "          #((5000000-5000000/2) * 1ps);\n"        ,
    "       the_clock=~the_clock;\n"                   ,
    "     end\n"                                       ,
    "   end\n"                                         ,
    "join_none\n"};

    `uvm_info("record_key_control_map_and_record", $sformatf("Start recording of interface if_record_key_control"), UVM_DEBUG);
    $fdisplay ( mcd0,tmg);