Is there a simple example of how to generate verilog from Chisel3 module?

Question

I'm looking for a simple howto to convert a simple Chisel3 module in Verilog.

I take Gcd source code given on official web page of chisel.

  import chisel3._

  class GCD extends Module {
    val io = IO(new Bundle {
      val a  = Input(UInt(32.W))
      val b  = Input(UInt(32.W))
      val e  = Input(Bool())
      val z  = Output(UInt(32.W))
      val v  = Output(Bool())
    })
    val x = Reg(UInt(32.W))
    val y = Reg(UInt(32.W))
    when (x > y) {
      x := x -% y
    }.otherwise {
      y := y -% x
    }
    when (io.e) {
      x := io.a
      y := io.b
    }
    io.z := x
    io.v := y === 0.U
  }

I can't find a how to write a build.sbt and class instantiation for converting it in Verilog.

Answer 1

Thank you for your interest in Chisel! We generally encourage people to use our chisel-template repo as a starting point for Chisel3 projects: https://github.com/ucb-bar/chisel-template

If you want to do the most barebones possible thing. Create this build.sbt and put it in the root directory for your project.

scalaVersion := "2.12.13"

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.4"

Put the above GCD source code in GCD.scala and add the following to the file:

import chisel3.stage.ChiselStage

object GCDDriver extends App {
  (new ChiselStage).emitVerilog(new GCD, args)
}

You can then generate the Verilog by running: sbt "runMain GCDDriver". The default output directory is the current directory.

You can see what command-line options are available by running sbt "runMain GCDDriver --help" For example --target-dir will let you change the target directory