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Verilog Always block using (*) symbol

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verilog

I have a simple question regarding how to write an always block in a Verilog module.
If I have the following inputs in my Verilog module:

input        [31:0] PCplus4 ;       // Value of PC + 4
input        [31:0] A;          // Value A, i.e. RSbus (Use Forwarded Value)
input        [31:0] B;          // Value B, i.e. RTbus (Use Forwarded Value)
input        [31:0] IMM;            // Extended Immediate Value
input        [25:0] TARGET;         // Target Address for Jumps
input         [3:0] BR;         // Branch Selector Input

Is there any difference if I use

always @ (*)  

instead of

always @ (PCplus4  or A or B or IMM or TARGET or BR)  

Is this always @ (*) syntax valid for all versions of Verilog?

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all_by_grace Avatar asked May 15 '11 17:05

all_by_grace


People also ask

What does always (*) mean in Verilog?

The (*) means "build the sensitivity list for me". For example, if you had a statement a = b + c; then you'd want a to change every time either b or c changes. In other words, a is "sensitive" to b & c . So to set this up: always @( b or c ) begin a = b + c; end.

What is the purpose of * in the sensitivity list in Verilog?

Verilog-2001 adds a new wild card token, @*, which represents a combinational logic sensitivity list. The @* token adds to the sensitivity list all nets and variables that are read by the statements in the always block.

What is the always block in Verilog?

In Verilog, the always block is one of the procedural blocks. Statements inside an always block are executed sequentially. The sensitive list is the one that tells the always block when to execute the block of code.

What does the sensitivity list * mean to the Verilog compiler?

In hardware description languages (HDL), sensitivity lists are used to indicate which events may trigger a VHDL process or (System)Verilog always statement. These trigger events are usually transitions of signals that are inputs of the process or always statement.


1 Answers

The always @(*) syntax was added to the IEEE Verilog Std in 2001. All modern Verilog tools (simulators, synthesis, etc.) support this syntax.

Here is a quote from the LRM (1800-2009):

An incomplete event_expression list of an event control is a common source of bugs in register transfer level (RTL) simulations. The implicit event_expression, @*, is a convenient shorthand that eliminates these problems by adding all nets and variables that are read by the statement (which can be a statement group) of a procedural_timing_ control_statement to the event_expression.

So, your two lines of code may be equivalent (it depends on the code in the body of your always block). However, the @* syntax is easier to maintain.

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toolic Avatar answered Oct 15 '22 03:10

toolic