Is there something like __LINE__ in Verilog?

Question

I am new to Verilog but have been a C programmer for years which makes me dangerous.

I'm doing some Verilog for a class. I'd like to use C assert() style testing in my simulation code. https://en.wikipedia.org/wiki/Assert.h

We aren't using System Verilog so there is no standard assert that I could find. I have cobbled together the following macro.

`define ASSERT_EQUALS(x,y) \
    repeat(1)\
    begin\
        if( (x) != (y) ) \
        begin\
            $write( "assert failed %d != %d\n", (x), (y) );\
            $finish;\
        end\
    end 

    // test the assert( should fail)
    `ASSERT_EQUALS(t_data_in,16'hfffe)

As far as I can tell there is no way to get a line number. So if the assertion fails, I only get a message with no way to link back to the location of the failure.

assert failed 65535 != 65534

Is there a way to get the current line number? Or is there a better way to do an assertion test in Verilog?

Thanks!

Answer 1

SystemVerilog 2009 offers compiler directives. Quoting from the specification IEEE Std 1800-2009, Section 22.13:

`__FILE__ expands to the name of the current input file, in the form of a string literal. This is the path by which a tool opened the file, not the short name specified in `include or as a tool’s input file name argument. The format of this path name may be implementation dependent.

`__LINE__ expands to the current input line number, in the form of a simple decimal number.

For example:
$display("Internal error: null handle at %s, line %d.", `__FILE__, `__LINE__);

Refer to the full specification for more details.