Assign integer to reg in Verilog

Question

I have problems with this Verilog code. Basically, it won't let me do the Y = 3'di statement. Basically, I want Y to equal i. I am pretty sure the problem is the i. So, is there a way to do this in Verilog? Also, W is an input with 8 bits (in other words, W[7:0]).

for (i = 7; i >= 0; i = i - 1)
begin
    if(W[i]) Y=3'di;
end

Thanks.

Answer 1

You can select bits using brackets .

for (i = 7; i >= 0; i = i - 1)
begin
    if(W[i]) Y = i[2:0];
end

But it isn't even necessary if i was declared to be an integer. It will take however many bits fit in Y automatically and you only wanted the LSBs.

Answer 2

You might wish to use a case statement here:

case (1'b1)
  W[0]: Y=3'd0;
  W[1]: Y=3'd1;
  W[2]: Y=3'd2;
  W[3]: Y=3'd3;
  W[4]: Y=3'd4;
  W[5]: Y=3'd5;
  W[6]: Y=3'd6;
  W[7]: Y=3'd7;
  default: Y=3'd0; // to avoid inferring a latch when W==8'd0
endcase

This makes the priority more obvious to readers of your code.