Program to create a Verilog block diagram

Question

I want to create a program to parse Verilog and display a block diagram. Can someone help me regarding what algorithms I need to look into? I found a good Verilog parser, but now I need to find the relation between each block and place them accordingly. It does not have to be extensively optimized.

UPDATE:

for now I am using ironPython to draw the block diagram in Visio.

1. Create a list of blocks with their inputs and outputs
2. Create a graph which matches all the outputs of a block to their corresponding inputs. This basically has all the connections between blocks.
3. Find a place for them in the Visio diagram.
4. Draw them on Visio
5. Connect them on Visio.

Answer 1

Yosys is an open source verilog synthesis tool. It can also be used to analyze designs and create schematics (using GraphViz). See the screenshots on the webpage:

• http://www.clifford.at/yosys/screenshots.html

If I understand your requirements correctly, Yosys already does what you want. If you still want to write your own program, you could use Yosys as a reference to get you started.

(Conflict of Interest Disclosure: I am the author of Yosys.)

Answer 2

You could try using the Altera synthesis too, EASE, HDL designer, Synplify HDL Analyst, nSchema, or Xilinx PlanAhead.