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What is the difference between = and <= in Verilog?

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verilog

What is the difference between = and <= in this code? Also, how do I print the value of data?

    module always_example();
reg clk,reset,enable,q_in,data;

always @ (posedge clk)
if (reset)  begin
   data <= 0;
end else if (enable) begin   
   data <= q_in;
end
// if i put     $print("data=%d", data);   there is error
endmodule
like image 767
Hayder Al-Amily Avatar asked Feb 16 '16 14:02

Hayder Al-Amily


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Whats the difference between <= and in Verilog?

In an always block, the line of code will be executed only after it's previous line has executed. Hence, they happens one after the other, just like combinatoral logics in loop. <= is non-blocking in nature. This means that in an always block, every line will be executed in parallel.

What does <= mean in System Verilog?

"<=" is a non-blocking assignment operator in verilog. "=" is a blocking assignment operator.

What is the difference between == and === in Verilog?

In Verilog: == tests logical equality (tests for 1 and 0, all other will result in x) === tests 4-state logical equality (tests for 1, 0, z and x)

What is the difference between && and & in Verilog?

&& is logical AND. It accepts two booleans and returns boolean. & is bitwise AND. It accepts two numbers and returns a number.


1 Answers

= is blocking statement. In an always block, the line of code will be executed only after it's previous line has executed. Hence, they happens one after the other, just like combinatoral logics in loop.

<= is non-blocking in nature. This means that in an always block, every line will be executed in parallel. Hence leading to implementation of sequential elements.

like image 122
Sourabh Avatar answered Sep 21 '22 20:09

Sourabh