Difference between Behavioral, RTL and gate Level

Question

I'm trying to fully understand the differences between the abstraction levels of Verilog, I get what the description of each level says but I still can't get it on the play.

For this case, I will paste some Verilog codes and what I think about them:

1. The following code is in Behavioral Level.

   always  @ (a or b or sel)
     begin
       y = 0;
       if (sel == 0) begin
         y = a;
       end else begin
       y = b;
     end
   end
   

2. This (just an example) is in Gate Level

   module test(clk,  ready, next, Q);
     input clk, enable, next;
     output Q;
   
     \**SEQGEN** reg_1 (.clear(1'b0), .next_state(next), .clocked_on(clk), .Q(Q), .synch_enable(enable) );
   
   endmodule
   

3. I don't know if this code is in RTL or Gate Level ( I expect that the always keyword make this RTL and not Gate Level )

   module dff_from_nand();
     wire Q,Q_BAR;
     reg D,CLK;
   
     nand U1 (X,D,CLK) ;
     nand U2 (Y,X,CLK) ;
     nand U3 (Q,Q_BAR,X);
     nand U4 (Q_BAR,Q,Y);
   
     // Testbench of above code
     initial begin
       $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);
       CLK = 0;
       D = 0;
       #3  D = 1;
       #3  D = 0;
       #3  $finish;
     end   
   
     always  #2  CLK = ~CLK;
   
   endmodule
   

I already know that initial begin and end are not synthesizeable and just used for testing. Now I have 2 questions

1. Third (and second) code is RTL or Gate-Leve? What would be a good RTL code example? I found this RTL Code Example but is that really RTL? For me it looks like behavioral level.

2. What means Verilog netlist? Is it the same as gate level or it have a context base definition?

I'm confused because in some websites I don't know if they're saying 'this is a Verilog code that is using logic gates' or 'this is a Verilog code in gate-level'

I will be very happy if somebody who wants to explain more details about this topic :)

Answer 1

RTL : Register-Transfer-Level, an abstraction hardware functionality written with always blocks and assign statements that are synthesizable (can be translated into gate level). Pure RTL does not instantiate sub-modules. RTL could contain sub-modules to guide the synthesizer. Structural RTL (ofter still called RTL) is a module that contains other RTL modules. Example: FSM (Finite-State-Machine)

always @* begin
  next_state = state;
  if (count>0) next_count = count - 1;
  case (state)
  IDLE :
    if(do_start) begin
      next_state = START;
      next_count = 2;
    end
  START :
    if (do_wait) begin
      next_count = count;
    end
    else if (count==0) begin
      next_state = RUN;
      next_count = count_from_input;
    end
  RUN :
    if (do_stop) begin
      next_state = IDLE;
    end
    if (do_wait) begin
      next_count = count;
    end
    else if (count==0) begin
      next_state = IDLE;
    end
  endcase
end
always @(posedge clk, negedge rst_n) begin
  if (!rst_n) begin
    count <= 0;
    state <= IDLE;
  end
  else begin
    count <= next_count;
    state <= next_state;
  end
end

Behavioral : Mimics the desired functionality of the hardware but not necessarily synthesizable. There is no strict rules as long as the code generates the desired behavior. Guideline is to keep it simple and readable. Behavioral are often used to represent analog block, place holder code (RTL/gates not ready), and testbench code. Example: clock generator, delay cells.

always begin
  if (!clk_en && clk==1'b1) begin
    wait (clk_en);
  end
  #5 clk = ~clk;
end

The key difference between RTL and Behavioral is the ability to synthesize. It is behavioral if you see # delay, wait statements, while loops, force/release statements, or hierarchical reference. Technically there are some rare excusable exceptions, but that is out of scope if this question.

Gate-Level (aka Structural) : Logic described by gates and modules only. No always blocks or assign statements. This is a representative of the real gates in the hardware.

Verilog Netlist is a collection of Verilog modules used in the design. It can be one or many files. It can be a mix of of RTL, Behavioral and Structural. Usually it is mostly Structural, especially for large designs.

Answer 2

1. Behavioral level.
2. RTL level (don't have to be gate level, but primitive level.
3. A mixed working module/testbench, all enclosed in a single module. Not the best approach to design with Verilog, but would be OK for a teaching example. In fact, this example is actually two modules:

The testbench, which can be considered behavioral, even if it uses RTL coding to instantiate the module that is going to be tested to the regs and wires that the testbench drives:

module testbench_dff;
  wire Q,Q_BAR;
  reg D,CLK;

  // Instantiate the unit under test
  dff_from_nand uut (.CLK(CLK), .D(D), .Q(Q), .Q_BAR(Q_BAR) );

  // Testbench
  initial begin
    $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);
    CLK = 0;
    D = 0;
    #3  D = 1;
    #3  D = 0;
    #3  $finish;
  end   

  always  #2  CLK = ~CLK;

endmodule

The unit under test (UUT) being tested, which it's a module like this (which is clearly a RTL level -gate level actually- module):

module dff_from_nand (
  input wire CLK,
  input wire D,
  output wire Q,
  output wire Q_BAR
  );

  wire X,Y;
  nand U1 (X,D,CLK) ;
  nand U2 (Y,X,CLK) ;
  nand U3 (Q,Q_BAR,X);
  nand U4 (Q_BAR,Q,Y);
endmodule

It's my understanding that a RTL level module is a module in which logic equations are explicity given. Behavioral module has processes (in Verilog using always blocks, although logic equations can be used inside those blocks). Any non-trivial Verilog design will have both.