I have a test bench that monitors a bus. Some of signals within the bus can be 1'bx. For a variety of reasons I need to know if any of the signals within the bus are 1'bx. What's the best way to test (not for synthesis -- only for simulation purposes) if a bus contains any x's? I had hoped that I could use a reduction or and then use ===, but this doesn't seem to work. Thanks,
D
The right side 1'bX is a 1-bit wide literal that has all bits set to X . The operator === compares the sides, including equality of X and Z states.
$isunknown(expression) returns `true (bit 1'b1) if any bit of the expression is X or Z. This is equivalent to ^(expression) === 'bx. 4. $countones (expression) returns the number of ONEs in a bit vector expression.
“X” is used by simulators when a wire hasn't been initialized to a known value or when the predicted value is an illegitimate logic value (e.g., due to contention on a tri-state bus).
In Verilog: == tests logical equality (tests for 1 and 0, all other will result in x) === tests 4-state logical equality (tests for 1, 0, z and x)
(^bus === 1'bX)
Bit-wise xor the bus then check if the result is X. If any bit is X or Z then the result will be X.
To know which bit in the bus has the error:
always @* begin
for(integer i=0; i<$size(bus); i++) begin
if(bus[i]===1'bX) $display("bus[%0d] is X",bus[i]);
if(bus[i]===1'bZ) $display("bus[%0d] is Z",bus[i]);
end
end
You can use $isunknown
(refer to the IEEE Std 1800-2017, section 20.9 Bit vector system functions):
module tb;
reg [3:0] data;
initial begin
#5 data = 4'b0101;
#5 data = 4'b000x;
#5 data = 4'b1111;
#5 data = 4'b0x0x;
#5 data = 4'b0x1x;
#5 data = 4'bzzzz;
#5 $finish;
end
always @(data) begin
if ($isunknown(data)) $display($time, " data=%b has x's", data);
end
endmodule
Outputs:
10 data=000x has x's
20 data=0x0x has x's
25 data=0x1x has x's
30 data=zzzz has x's
Note that this also treats z
as x
.
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