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Is it possible to instantiate a module conditionally in verliog ?
example :
if (en==1)
then module1 instantiation
else
module2 instantiation
692
When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances.
Verilog generate statement is a powerful construct for writing configurable, synthesizable RTL. It can be used to create multiple instantiations of modules and code, or conditionally instantiate blocks of code.
You can't instantiate a module conditionally within an if statements (*), and you definitely can't instantiate them within procedural blocks.
Hardware modules may not be instantiated inside an always block. All of the always blocks in a module are considered to be parallel blocks of hardware. Likewise, modules are considered to be separate hardware blocks that operate in parallel. Functions, however, can be instantiated in an always block.
Verilog Module Instantiations As we saw in a previous article, bigger and complex designs are built by integrating multiple modules in a hierarchical manner. Modules can be instantiated within other modules and ports of these instances can be connected with other signals inside the parent module.
A generate block allows to multiply module instances or perform conditional instantiation of any module. It provides the ability for the design to be built based on Verilog parameters.
Syntax: Module instantiation consists of module_name followed by instance_name and port_association_list. Need of instance_name is, we can have multiple instance of same module in the same program. Instance name should be unique for each instance of the same module. Port_association_list shows how ports are mapped.
to choose an instantiation at compile time. If in you are asking if you can instantiate a module based on a wire value, no you cannot do that. Show activity on this post.
From IEEE Std 1364-2001 :
12.1.3.3 generate-conditional A generate-conditional is an if-else-if generate construct that permits modules, user defined primitives, Verilog gate primitives, continuous assignments, initial blocks and always blocks to be conditionally instantiated into another module based on an expression that is deterministic at the time the design is elaborated.
example given in LRM :
module multiplier(a,b,product);
parameter a_width = 8, b_width = 8;
localparam product_width = a_width+b_width; // can not be modified
// directly with the defparam statement
// or the module instance statement #
input [a_width-1:0] a;
input [b_width-1:0] b;
output [product_width-1:0] product;
generate
if((a_width < 8) || (b_width < 8))
CLA_multiplier #(a_width,b_width) u1(a, b, product);
// instantiate a CLA multiplier
else
WALLACE_multiplier #(a_width,b_width) u1(a, b, product);
// instantiate a Wallace-tree multiplier
endgenerate
// The generated instance name is u1
endmodule
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