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I tried to figure out the inferred latch and why it is needed internally, but I couldn't find any resources with enough detail.
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A latch is inferred when the output of combinatorial logic has undefined states, that is it must hold its previous value. Combinatorial logic does not have any flip-flop to hold state therefore the output should always be defined by the inputs.
Latch inference refers to the condition whereby latches are inserted by synthesis tool to enable a signal to maintain its previous value. Inferring latches in a design is not desirable as it unnecessarily increases the size of the design. A bigger design will translate to a higher cost.
Latches are inferred in VHDL by using the IF statement without its matching ELSE. This causes the synthesis to make the logical decision to “hold” the value of a signal when not told to do anything else with it. The inferred latch is a transparent latch.
Latches are created when you create a combinational process or conditional assignment (in VHDL) or a combinational always block (in Verilog) with an output that is not assigned under all possible input conditions. This creates what is known as incomplete assignment by the synthesis tools.
A latch is inferred when the output of combinatorial logic has undefined states, that is it must hold its previous value.
Combinatorial logic does not have any flip-flop to hold state therefore the output should always be defined by the inputs.
A short example might be:
always @* begin
if (a == 1'b1) begin
b = x|y|z;
end
end
What is b when a == 1'b0. b is not being overridden so it would hold its value. How can something hold its value when it does not have the concept of state. You have to introduce state by inferring a latch. This is normally a really bad thing.
You can imply latches and be carefull about the timing etc but inferred latches are nominally from buggy code.
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