I am trying to use Quartus II 13.0 (Free Web Package) on Linux (Kubuntu 12.04 LTS) from the command line to generate Verilog technology netlists from Verilog RTL. I need this for a project where I compare the synthesis results produced by different tools for thousands of generated Verilog files. So using the GUI is not really an option..
For example with Xilinx Vivado I can do that using the following TCL commands:
read_verilog input.v
synth_design -part xc7k70t -top top_module
write_verilog output.v
Most ASIC tools I have worked with provide similar interfaces.
With Xilinx XST it is a bit more complicated:
1.) generation of a work.xst file:
run -ifn work.prj ..some..more..options..
2.) generation of a work.prj file:
verilog work "input.v"
3.) running synthesis:
xst -ifn work.xst
4.) generating verilog netlist from verilog binary:
netgen -w -ofmt verilog work.ngc output
But with Quartus II I can't find any documentation at all on how to use the command line tools. All I can find is documentation to the graphical IDE interface. Maybe I'm just looking in the wrong places?
So before I start poking the Quartus II IDE with strace and similar tools: Is anyone using Quartus II from the command line and can point me in the right direction?
It's very well hidden - Quartus-II Handbook Version 13.0, page 2-10 (or search ASSIGNMENT_FILES) - produces one example Makefile. It seems to have bit-rot - I've removed the ASSIGNMENT_FILES stuff, and the stamps are redundant (you can check for logfiles), but it's a start, and the basic structure works.
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With